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M25P20
2 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface
FEATURES SUMMARY s 2 Mbit of Flash Memory
s
Figure 1. Packages
Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (512 Kbit) in 2 s (typical) Bulk Erase (2 Mbit) in 3 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 MHz Clock Rate (maximum) Deep Power-down Mode 1 A (typical) Electronic Signature (11h) More than 100,000 Erase/Program Cycles per Sector More than 20 Year Data Retention
s s s s s s s s
8 1
SO8 (MN) 150 mil width
s
VFQFPN8 (MP) (MLP8)
December 2002
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M25P20
SUMMARY DESCRIPTION The M25P20 is a 2 Mbit (256K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram
VCC
Figure 3. SO and VFQFPN Connections
M25P20 S Q W VSS 1 2 3 4 8 7 6 5
AI04081B
VCC HOLD C D
D C S W HOLD M25P20
Q
Note: 1. See page 30 (onwards) for package dimensions, and how to identify pin-1.
VSS
AI04080
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
S
W HOLD VCC VSS
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SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
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SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - CPOL=0, CPHA=0 - CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: - C remains at 0 for (CPOL=0, CPHA=0) - C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device SPI Memory Device CQD CQD
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL
CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceeded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (S) is Low, the device is enabled, and in the Active Power mode. When Chip Select (S) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to I CC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertant Write, Program or Erase instructions. Status Register The Status Register contains a number of status and control bits, as shown in Table 5, that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
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Protection Modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P20 boasts the following data protection mechanisms: s Power-On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification.
s
- Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion
s
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W) signal, in co-operation with the Status Register Write Disable (SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be write-protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertant Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Powerdown instruction).
s
Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion
s
s
Table 2. Protected Area Sizes
Status Register Content BP1 Bit 0 0 1 1 BP0 Bit 0 1 0 1 none Upper quarter (Sector 3) Upper half (two sectors: 2 and 3) All sectors (four sectors: 0, 1, 2 and 3) Protected Area Memory Content Unprotected Area All sectors1 (four sectors: 0, 1, 2 and 3) Lower three-quarters (three sectors: 0 to 2) Lower half (Sectors 0 and 1) none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.
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Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 6). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the Figure 6. Hold Condition Activation
rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 6). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition.
C
HOLD
Hold Condition (standard use)
Hold Condition (non-standard use)
AI02029D
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MEMORY ORGANIZATION The memory is organized as: s 262,144 bytes (8 bits each)
s s
Table 3. Memory Organization
Sector 3 2 1 0 Address Range 30000h 20000h 10000h 00000h 3FFFFh 2FFFFh 1FFFFh 0FFFFh
4 sectors (512 Kbits, 65536 bytes each) 1024 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
256 Byte Data Buffer
Status Register
3FFFFh
30000h
Y Decoder
20000h
Size of the read-only memory area
10000h
00000h 256 Bytes (Page Size) X Decoder
000FFh
AI04079
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INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (S) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Electronic Signature Table 4. Instruction Set
Instruction WREN WRDI RDSR WRSR READ Description Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes One-byte Instruction Code 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 Address Bytes 0 0 0 0 3 3 3 3 0 0 0 1010 1011 0 0 Dummy Bytes 0 0 0 0 0 1 0 0 0 0 3 Data Bytes 0 0 1 to 1 1 to 1 to 1 to 256 0 0 0 1 to 0
(RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
FAST_READ Read Data Bytes at Higher Speed PP SE BE DP Page Program Sector Erase Bulk Erase Deep Power-down Release from Deep Power-down, and Read Electronic Signature Release from Deep Power-down
RES
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Figure 8. Write Enable (WREN) Instruction Sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
Write Enable (WREN) The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High.
Figure 9. Write Disable (WRDI) Instruction Sequence
S 0 C Instruction D High Impedance Q
AI03750D
1
2
3
4
5
6
7
Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:
- Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion
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Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10.
Table 5. Status Register Format
b7 SRWD 0 0 0 BP1 BP0 WEL b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are 0. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.
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Figure 11. Write Status Register (WRSR) Instruction Sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle
(whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.
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Table 6. Protection Modes
W Signal 1 0 SRWD Bit 0 0 Software Protected (SPM) Mode Write Protection of the Status Register Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the SRWD, BP1 and BP0 bits cannot be changed Memory Content Protected Area1 Unprotected Area1
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
1
1
0
1
Hardware Protected (HPM)
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 6. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): - If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. - If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
(Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: - by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low - or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
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Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI03748D
Note: 1. Address bits A23 to A18 are Don't Care.
Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the
next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
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Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
Note: 1. Address bits A23 to A18 are Don't Care.
Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the
next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
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Figure 14. Page Program (PP) Instruction Sequence
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 2072 2073 2074 2075 2076 2077 2 2078 1 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3 Data Byte 256 2079 0
AI04082B
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
MSB
MSB
Note: 1. Address bits A23 to A18 are Don't Care.
Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256
data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the selftimed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see Tables 3 and 2) is not executed.
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Figure 15. Sector Erase (SE) Instruction Sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
Note: 1. Address bits A23 to A18 are Don't Care.
Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see Tables 3 and 2) is not executed.
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M25P20
Figure 16. Bulk Erase (BE) Instruction Sequence
S 0 C Instruction D 1 2 3 4 5 6 7
AI03752D
Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched
in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
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M25P20
Figure 17. Deep Power-down (DP) Instruction Sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
AI03753D
Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from I CC1 to I CC2, as specified in Table 12). Once the device has entered the Deep Powerdown mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction also allows the Electronic Signa-
ture of the device to be output on Serial Data Output (Q). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
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M25P20
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence
S 0 C Instruction 3 Dummy Bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
D High Impedance Q
23 22 21 MSB
3
2
1
0 Electronic Signature Out 7 MSB Deep Power-down Mode Stand-by Mode
AI04047C
6
5
4
3
2
1
0
Release from Deep Power-down and Read Electronic Signature (RES) Once the device has entered the Deep Powerdown mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature of the device. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. This instruction serves a second purpose. The device features an 8-bit Electronic Signature, whose value for the M25P20 is 11h. This can be read using the Release from Deep Power-down and Read Electronic Signature (RES) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 18. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic Signature to be output repeatedly. When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S) must remain High for at least tRES2(max), as specified in Table 13. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
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M25P20
Figure 19. Release from Deep Power-down (RES) Instruction Sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tRES1
High Impedance Q Deep Power-down Mode Stand-by Mode
AI04078B
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 19), still insures that the device is put into Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If
the device was previously in the Deep Powerdown mode, though, the transition to the Stand-by Power mode is delayed by t RES1, and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 13. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
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M25P20
POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until V CC reaches the correct value: - VCC(min) at Power-up, and then for a further delay of tVSL - VSS at Power-down Usually a simple pull-up resistor on Chip Select (S) can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while V CC is less than the POR threshold value, V WI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that V CC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: Figure 20. Power-up Timing
VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL Read Access allowed Device fully accessible
- tPUW after VCC passed the V WI threshold - tVSL afterVCC passed the VCC(min) level These values are specified in Table 7. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: - The device is in the Standby mode (not the Deep Power-down mode). - The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stablise the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1F). At Power-down, when VCC drops from the operating voltage, to below the POR threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
time
AI04009C
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M25P20
Table 7. Power-Up Timing and VWI Threshold
Symbol tVSL
1
Parameter VCC(min) to S low Time delay to Write instruction Write Inhibit Voltage
Min. 10 1 1
Max.
Unit s
tPUW1 VWI1
10 2
ms V
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status Register bits are 0).
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M25P20
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 8. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VESD Storage Temperature Lead Temperature during Soldering (20 seconds max.)1 Input and Output Voltage (with respect to Ground) Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 SO VFQFPN -0.6 -0.6 -2000 Parameter Min. -65 Max. 150 235 235 4.0 4.0 2000 Unit C C C V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M25P20
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 9. Operating Conditions
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 2.7 -40 Max. 3.6 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 10. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 30
Max.
Unit pF
5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
ns V V
Figure 21. AC Measurement I/O Waveform
Input Levels 0.8VCC
Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 11. Capacitance
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V Min. Max. 8 6 Unit pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 20 MHz.
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M25P20
Table 12. DC Characteristics
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Standby Current Deep Power-down Current Operating Current (READ) Operating Current (PP) Operating Current (WRSR) Operating Current (SE) Operating Current (BE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -100 A VCC-0.2 S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open S = VCC S = VCC S = VCC S = VCC - 0.5 0.7VCC Test Condition (in addition to those in Table 9) Min. Max. 2 2 50 5 4 15 15 15 15 0.3VCC VCC+0.4 0.4 Unit A A A A mA mA mA mA mA V V V V
Table 13. AC Characteristics
Test conditions specified in Table 9 and Table 10 Symbol fC fR tCH 1 tCL 1 tCLCH 2 tCHCL 2 tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ 2 tCLQV tCSH tDIS tV tDSU tDH tCSS tCLH tCLL Alt. fC Parameter Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock Frequency for READ instructions Clock High Time Clock Low Time Clock Rise Time3 (peak to peak) Clock Fall Time3 (peak to peak) S Active Setup Time (relative to C) S Not Active Hold Time (relative to C) Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C) S Deselect Time Output Disable Time Clock Low to Output Valid Min. D.C. D.C. 18 18 0.1 0.1 10 10 5 5 10 10 100 15 15 Typ. Max. 25 20 Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns
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M25P20
Test conditions specified in Table 9 and Table 10 Symbol tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX 2 tHLQZ 2 tWHSL 4 tSHWL 4 tDP 2 tRES1 2 tRES2 2 tW tPP tSE tBE tLZ tHZ Alt. tHO Output Hold Time HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD to Output Low-Z HOLD to Output High-Z Write Protect Setup Time Write Protect Hold Time S High to Deep Power-down Mode S High to Standby Mode without Electronic Signature Read S High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Page Program Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time 5 1.5 2 3 20 100 3 3 1.8 15 5 3 6 Parameter Min. 0 10 10 10 10 15 20 Typ. Max. Unit ns ns ns ns ns ns ns ns ns s s s ms ms s s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
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M25P20
Figure 22. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W tWHSL
tSHWL
S
C
D High Impedance Q
AI07439
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M25P20
Figure 24. Hold Timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
Figure 25. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449D
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M25P20
PACKAGE MECHANICAL SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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M25P20
VFQFPN8 - 8-contact Very-thin Fine-pitch QFP No-lead, Package Outline
D D1
E E1
E2
e
b A A2 L D2
A1 A3
VFQFPN-01
Note: Drawing is not to scale.
VFQFPN8 - 8-contact Very-thin Fine-pitch QFP No-lead, Package Mechanical Data
mm Symb. Typ. A A1 A2 A3 b D D1 D2 E E1 E2 e L 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.60 0.50 0.75 12 3.80 4.20 3.20 3.60 0.35 0.48 0.85 0.00 Min. Max. 1.00 0.05 0.0256 0.0079 0.0157 0.2362 0.2264 0.1339 0.1969 0.1870 0.1575 0.0500 0.0236 0.0197 0.0295 12 0.1496 0.1654 0.1260 0.1417 0.0138 0.0189 Typ. 0.0335 0.0000 Min. Max. 0.0394 0.0020 inches
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M25P20
PART NUMBERING Table 14. Ordering Information Scheme
Example: Device Type M25P Device Function 20 = 2 Mbit (256K x 8) Operating Voltage V = VCC = 2.7 to 3.6V Package MN = SO8 (150 mil width) MP = VFQFPN8 (MLP8) Temperature Range 6 = -40 to 85 C Option T = Tape & Reel Packing M25P20 - V MN 6 T
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M25P20
REVISION HISTORY Table 15. Document Revision History
Date 12-Apr-2001 25-May-2001 Rev. 1.0 1.1 Document written Serial Paged Flash Memory renamed as Serial Flash Memory Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes; Release from Power-down and Read Electronic Signature (RES); Power-up Repositioning of several tables and illustrations without changing their contents Power-up timing illustration; SO8W package removed Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL FAST_READ instruction added. Document revised with new timings, VWI, ICC3 and clock slew rate. Descriptions of Polling, Hold Condition, Page Programming, Release for Deep Powerdown made more precise. Value of tW(max) modified. Clarification of descriptions of entering Stand-by Power mode from Deep Power-down mode, and of terminating an instruction sequence or data-out sequence. VFQFPN8 package (MLP8) added. Document promoted to full datasheet. Typical Page Program time improved. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after. Description of Revision
11-Sep-2001
1.2
16-Jan-2002
1.3
16-May-2002 12-Sep-2002 13-Dec-2002
1.4 1.5 1.6
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M25P20
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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